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Creators/Authors contains: "Boynton, Zachariah"

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  1. ; ; ; ; ; ; (, IEEE 47th European Solid State Circuits Conference (ESSCIRC))
    All-digital millimeter-wave (mmWave) massive multi-user multiple-input multiple-output (MU-MIMO) receivers enable extreme data rates but require high power consumption. In order to reduce power consumption, this paper presents the first resolution-adaptive all-digital receiver ASIC that is able to adjust the resolution of the data-converters and baseband-processing engine to the instantaneous communication scenario. The scalable 32-antenna, 65 nm CMOS receiver occupies a total area of 8 mm 2 and integrates analog-to-digital converters (ADCs) with programmable gain and resolution, beamspace channel estimation, and a resolution-adaptive processing-in-memory spatial equalizer. With 6-bit ADC samples and a 4-bit spatial equalizer, our ASIC achieves a throughput of 9.98 Gb/s while being at least 2× more energy-efficient than state-of-the-art designs. 
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  2. ; ; ; (, Synthetic Diversity To Mitigate Out-of-Band Interference in Widely Tunable Wireless Receivers)
    null (Ed.)
    Here we present a combined RF hardware/DSP technique to synthesize effective channel diversity in single-antenna wireless systems. This allows digital suppression of out-of-band interference artifacts in widely tunable wireless receivers with one or more antennas, including artifacts from LO phase noise. A passive inductor-capacitor (LC) network provides gain and phase diversity between channels and across frequency. Since amplitude and phase of in-band artifacts are set by the amplitude and phase of the out-of-band interference that generates them, they can be suppressed in DSP without knowledge about the interferer itself. The feasibility of this approach is demonstrated mathematically, with numerical system simulations, and full circuit simulation. 
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  3. ; ; ; ; (, IEEE Transactions on Circuits and Systems I: Regular Papers)
    null (Ed.)
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  4. ; ; ; ; (, IEEE Transactions on Circuits and Systems I: Regular Papers)
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  5. ; ; ; ; ; (, 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC))
    A highly-integrated dual technology (28nm and 130nm SOI) widely tunable software-defined RF duplexing front-end for FDD, FD, and TDD applications is presented. Predistortion and harmonic upconversion are used to cancel second and third harmonics generated by PA nonlinearity by up to 30 dB. A novel form of non-reciprocal, distributed degeneration is used to suppress TX noise that desensitizes the RX for full duplex operation. The distributed degeneration network improves RX noise figure by 7dB over baseline TX operation for same channel TX-RX. The transceiver achieves a 23dBm output power while maintaining more than 30dB of TX-RX isolation over the 0.8-1.2GHz band. 
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